School of Computer Science
University of Guelph, Guelph, ON N1G 2W1
StarPlace is a Field Programmable Gate Array (FPGA) analtyic placement tool. FPGAs are reprogrammable chips that can implement a wide range of digital circuits. In the process of mapping a digital circuit onto an FPGA, a very important, but time-consuming problem, called placement, must be solved. The input to the placement problem is a circuit netlist specifying the various types of logic blocks to be implemented and the interconnections between them. The result of placement is the mapping of all blocks onto physical resources on the target FPGA in a way that minimizes one or more objectives. StarPlace seeks to minimize the two most basic objectives: total wirelength and critical-path delay. When compared to VPR -- the state of the art academic placer -- StarPlace obtains an 8-9% reduction in critical-path delay while achieving a speedup of nearly 5x when VPR is run in its "fast" mode.
Pilot is a new method of programming High-Performance Computing (HPC) clusters that leverages standard Message-Passing Interface (MPI) while being easier for novice users to understand andutlize. MPI's large and daunting API presents multiprogramming hazards that even trained programmers find difficult to cope with (such as deadlock). In such instances detecting the condition, let along diagnosing the cause is overly challenging for scientific programmers. In Pilot, formal elements of Concurrent Sequental Processes (CSP), valuable for creating a sound theoretical basis, are kept "under the hood" of an "stdio.h-inspired" interface to avoid intimidating users with the need to learn a process algebra. In short, the goal of this work is to make HPC programming more accessible and hazard-free for scientific users. Pilot Download