Shawki Areibi

Headshot of Shawki Areibi
School of Engineering
Phone number: 
(519) 824-4120 ext. 53819
THRN 2335
Seeking academic or industry partnerships in the area(s) of: 
FPGA CAD and Electronic Design Automation.
Available positions for grads/undergrads/postdoctoral fellows: 
Please see Dr. Areibi’s School of Engineering profile for opportunities.

Education and Employment Background

Dr. Shawki M. Areibi received his PhD from the University of Waterloo in 1994. Following that, he spent several years working in industry as a computer engineer and research mathematician. In 1997, he held a position as an assistant professor at Ryerson University. Areibi joined the School of Engineering at the University of Guelph in 1999 where he is now a full professor.

Research Themes

Areibi’s research focuses on the development of algorithmic solutions for Very Large-Scale Integration (VLSI) physical design automation using mathematical programming and advanced search heuristics. Key areas of interest include:

  1. Physical design automation. VLSI circuit layout refers to those integrated circuits that contain more than one million transistors. This research deals with the algorithms that are used inside VLSI design automation tools, also called computer-aided design (CAD) tools. Areibi’s most recent work in this area integrated machine learning and deep learning into the CAD flow to enable it to make smart decisions.
  2. VLSI design. This research involves packing more and more logic devices into smaller and smaller areas. Areibi is motivated by the challenges of deep-submicron (DSM) integrated processes. These challenges stem from previously ignorable physical phenomena (signal propagation delay, mounting leakage currents, parameter variations, signal integrity), as well as the growing complexity of realizable VLSI systems.
  3. Reconfigurable computing systems. Reconfigurable computing systems are computers based on hardware, most of which can be arbitrarily defined to suit the needs of the problem to be solved. The goal of configurable computing is to achieve the performance of custom architectures while retaining the flexibility of general-purpose computing. Areibi seeks to design state of the art hardware accelerators to speed up the performance of combinatorial optimization heuristics and control algorithms based on tabu search, genetic algorithms, neural networks and fuzzy logic. 
  4. Hardware/software co-design for embedded systems. Embedded controllers for reactive real-time applications are implemented as mixed software-hardware systems. Generally, software is used for features and flexibility, while hardware is used for performance. Current methods for designing embedded systems require the specification of hardware and software separately. Areibi has developed a methodology for specification, automatic synthesis and validation of this sub-class of embedded systems.
  5. Algorithms and meta heuristic-based techniques for optimization. Combinatorial optimization study problems are characterized by a finite number of feasible solutions. Areibi has proposed novel techniques to reduce the complexity of problems via clustering and partitioning, as well as hybrid approaches that were very effective in solving combinatorial optimization problems in general and circuit layout.
  6. Digital signal processor (DSP)-based application (hearing aids). Embedded systems and mobile devices are often used in noisy environments, which leads to a reduction in the intelligibility and sound quality. Traditional design methods for noise reduction have focused on algorithm development followed by modifications for implementation on a general-purpose DSP. Advancements in field programmable gate arrays (FPGAs) provide new options for DSP design engineers.


  • Major funding, Awards, National or International Recognition, Prestigious affiliations, Memberships on editorial boards or societies
  • Engineering Society University of Guelph, Professor of the Year Award, 2019
  • Best paper Awards in the International Conference on Field-Programmable Logic and Applications (FPL), 2018; FPL 2019; the International Conference on Mechatronics, 2019
  • Senior Member of the Institute of Electrical and Electronics Engineers, 1995–2018
  • NSERC Engage Grant “Design Exploration of Cryptographic Accelerators,” 2017
  • Technical program committee member, Design Automation Conference, 2017