Seminar: Electronic Design Automation

High-Level Synthesis – The Right Side of History
Speaker: Jason Anderson
 

Abstract: High-level synthesis (HLS) was first proposed in the 1980s. After spending decades on the sidelines of mainstream RTL digital design, there has been tremendous buzz around HLS technology in recent years. Indeed, HLS is on the upswing as a design methodology for field-programmable gate arrays (FPGAs) to improve designer productivity and ultimately, to make FPGA technology accessible to software engineers having limited hardware expertise. The hope is that down the road, software developers could use HLS to realize FPGA-based accelerators customized to applications that work in tandem with standard processors to raise computational throughput and energy efficiency. And, the further hope is that such HLS-generated accelerators operate close to the speed and energy efficiency of human-expert-designed accelerators. In this talk, I will overview the trends behind the recent drive towards FPGA HLS and why the need for, and use of, HLS will only become more pronounced in the coming years. I will argue that HLS, as opposed to traditional RTL design, is on the “right side of history”. The talk will highlight current HLS research directions and expose some of the challenges for HLS that may hinder its update in the digital design community. I will also describe work underway in the LegUp HLS project at the University of Toronto - a publicly available HLS tool that has been downloaded by over 5000 groups from around the world.

Speaker: Jason Anderson is a Professor with the Dept. of Electrical and Computer Engineering, University of Toronto, and holds the Jeffrey Skoll  Endowed Chair. He joined the FPGA Implementation Tools Group, Xilinx, Inc., San Jose, CA, USA, in 1997, where he was involved in placement, routing, and synthesis. He became a Principal Engineer at Xilinx in 2007 and joined the university in 2008. His research interests are all aspects of tools, architectures, and circuits for FPGAs. He has co-authored over 80 peer-reviewed research publications, holds 29 U.S. patents and was Program Co-Chair for FPL 2016, Program Chair for ACM FPGA 2017, and is General Chair for ACM FPGA 2018.