Gary Grewal

Photo of Gary Grewal
Associate Professor
Phone number: 
Reynolds 2208

My research is highly interdisciplinary and spans both Computer Science and Computer Engineering. Specific research interests include developing computer-aided design tools to efficiently map digital hardware designs onto FPGAs, developing novel methods based on machine-learning, deep-learning, and reinforcement learning to solve key optimization problems within FPGA flows, reconfigurable computing, hardware acceleration, and parallel programming.

  • FPGA Architecture

  • FPGA Placement and Routing

  • Machine Learning

  • Deep Learning

  • Reinforcement Learning

  • Reconfigurable Computing

  • Hardware Acceleration

  • Parallel Programming

D. Maarouff, A. Shamli, T. Martin, G. Grewal and S. Areibi, "A Deep-Learning Framework for Predicting Congestion During FPGA Placement," 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), Gothenburg, Sweden, 2020, pp. 138-144, doi: 10.1109/FPL50879.2020.00033.

Z. Abuowaimer, D. Maarouf, T. Martin, J. Foxcroft, G. Grewal, S. Areibi, and A. Vannelli, “GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures,” 2018 ACM Transactions on Design Automation and Electronic Systems, Vol. 23, No. 5, doi:10.1145/3233244.

T. Martin, D. Maarouf, Z. Abuowaimer, A. Alhyari, G. Grewal, and S. Areibi, “A Flat Timing-Driven Placement Flow for Modern FPGAs”, 2019 Proceedings of the 56th Annual Design Automation Conference, Article No. 4, pp. 1-6, doi: 10.1145/3316781.3317743.