Publication

Patents:

• R. Muresan, N. Muresan, “Electronic nose apparatus, "Canadian patent application serial no. 2,788,034, MT Ref:126645.0003"; US patent application, Pub. No.: US 2013/0061692 A1, Pub. Date: March 14, 2013.
• R. Muresan, S. Gregori, Current flattening and current sensing methods and devices, US Patent No. 7716502, Issue Date: May 11, 2010.

Refereed Journals and International Conference Publications:

• R. Muresan, "Self-decoupling CMOS battery cell for low-power security protection", Submitted to: Canadian Journal of ECE, March 2019.
• V. Lidkea, R. Muresan, S. Zhou, A. Al-Dweik, “Improving the security of cloud-based intelligent transportation systems,” To Appear in Proc. of IEEE CCECE 2019, Edmonton, Canada.
• G. Thoms, R. Muresan, A. Al-Dweik, "Design of a chaotic block cipher operation mode for intelligent transportation system", In Proc. of IEEE ICCE 2019, Las Vegas, USA, Jan 2019.
• L. Yang, R. Muresan, A. Al-Dweik, "Image-based visibility estimation algorithm for intelligent transportation systems", In IEEE Access, vol. 6, pp. 76728-76740, November 2018.
• A. Al-Dweik, R. Muresan, M. Mayhew, M. Lieberman, "IoT-based multifunctional scalable real-time enhanced road side unit for intelligent transportation systems", In Proc. of IEEE CCECE 2017, Windsor, May 2017.
• K. Kamal, R. Muresan, "Capacitive physically uncloanable function", In Proc. of IEEE CCECE 2017, Windsor, May 2017. 
• A. Al-Dweik, M. Mayhew, R. Muresan, S. Ali, and A. Shami, "Intelligent transportation system using adaptive speed limits," In IEEE Vehicular Technology Magazine, vol. 12, issue: 1, pp. 39-47, March 2017.
• M. Mayhew, R. Muresan, "Implementation of a decoupling based power analysis attack countermeasure," In IET Circuits, Devices & Systems, Online ISSN 1751-8598, 07 September 2016.
• M. Mayhew, R. Muresan, “An overview of hardware level power analysis attack countermeasures,” In Journal of Cryptographic Engineering, Springer, pp. 1-32, June 2016.
• R. Muresan, M. Mayhew, "Nanoscale CMOS battery cells for gate level on-chip security designs", In Electronics Letters Journal, November 2015.
• M. Mayhew, R. Muresan, "Modeling the effect of NMOS gate capacitance in an on-chip decoupling capacitor PAA countermeasure," In Proc. of IEEE MWSCAS 2014, Texas, August 2014.
• M. Mayhew, R. Muresan, "On-chip nanoscale capacitor decoupling architecture for hardware security", In IEEE Transactions on Emerging Topics in Computing, Special Issue on Emerging Nanoscale Architectures for Hardware Security, Trust and Reliability, February 2014.
• M. Lieberman, R. Muresan, S. Yang, D. Doyle, "Hilbert-Huang transform for feature extraction of temperature modulated MOS sensors", In The International Journal of Information Acquisition, Jan. 2014. Link to the paper: http://www.worldscientific.com/doi/abs/10.1142/S0219878913500149
• R. Muresan, M. Mayhew, On-chip decoupling architecture with variable nMOS gate capacitance for security protection,  In Proc. of IEEE MWSCAS 2013, pp 1342-1345, August 2013.
• H. Vahedi, R. Muresan, S. Gregori. “Design of secure microsystems using current-to-data dependency analysis” In The Open Journal of Circuits and Systems (CS), vol. 4, no. 2, pp. 137-146, April 17, 2013.
• S. Shariati, R. Muresan, A. Vannelli. “Energy monitoring system for security and power management applications,” In ICM 2012, pp. 1-4, Algeria, Dec. 2012.
• R. Muresan, “Power analysis attacks and ardware level countermeasures for cryptographic devices,” In the Journal of Recent Patents on Electrical & Electronic Engineering, Bentham Science Publishers, vol. 5, no. 3, Dec. 2012.
• M. Mayhew, R. Muresan. “Integrated capacitor switch box circuit for security protection,” In Proc. Of  ISCAS 2012, pp. 1452-1455, Seoul, Korea, 2012.
• H. Vahedi, S. Gregori, R. Muresan. "The effectiveness of a current flattening circuit as countermeasure against dpa attacks," In the Microelectronics Journal, vol. 42, pp. 180-187, Jan 2011.
• H. Vahedi, R. Muresan, S. Naik, "High precision system-on-chip energy management for battery life-optimization," In the Proc. of 17th IEEE ICECS 2010, Athens, Greece, Dec. 2010.
• R. Muresan, “Patents in power analysis attacks and their countermeasures for cryptographic devices,” In the Journal of Recent Patents in Electrical Eng, Bentham Science Publishers, pp. 177-185, Nov. 2010.
• A. Abu-Khundhair, R. Muresan, S. X. Yang, " FPGA based real-time adaptive fuzzy logic controller," In Proc. of IEEE Int. Conf. on Automation and Log., Hong-Kong, pp. 539-544, Aug. 2010.
• M. Mayhew, R. Muresan. (Oct 2009). “Low-power AES coprocessor in 0.18 µm CMOS technology for secure microsystems,” In Proc. of IEEE/CMC Microsystems and Nanoelectronics Research Conference, Ottawa, Canada, Oct. 2009.
• A. Abu-Khundhair, R. Muresan, S. X. Yang, “Fuzzy control of semi-active automotive suspensions,” In Proc. of IEEE ICMA 2009, pp. 2118-2122, Changchun, Jilin, China, Aug 2009.
• H.Vahedi, S. Gregori, R. Muresan, "On-chip power-efficient current flattening circuit," In Journal of Circuits, Systems, and Computers, vol. 18, nr. 3 pp. 565-579, May 2009.
• J. Best, R. Muresan, "Secure architecture for multi-purpose electronic passports," In Proc. of 3rd Workshop on Embedded Systems Security, Atlanta, Georgia, October 2008.
• R. Muresan, S. Gregori, "Protection circuit against differential power analysis attacks for smart cards," In IEEE Transactions on Computers (Special Issue on Purpose Hardware for Cryptography and Cryptanalysis), Vol. 57, No. 11, November 2008.
• H. Vahedi, S. Gregori, R. Muresan, "Improved current flattening circuit using current injection, voltage regulation, and frequency switching," In Proc. of IEEE CCECE, May 2008, pp. 2061-2065.
• R. Muresan, S. Gregori, "Analysis of current-to-data dependency in asynchronous cryptographic circuits," In Proc. of MWSCAS/NEWCAS, Montreal, August 2007.
• Z. Yang, R. Muresan: "The impact of the implementation style on power consumption and security in embedded cryptosystems", In Proc. of IEEE CCECE Ottawa, May 2006.
• D. Patel, R. Muresan: "Triple-DES ASIC module for a power-smart system-on-chip architecture," In Proc. of IEEE CCECE Ottawa, May 2006.
• H. Vahedi, R. Muresan, S. Gregori: "On-chip current flattening circuit with voltage scaling," In Proc. of IEEE ISCAS 2006, May, Kos, Greece.
• R. Muresan, C.Gebotys: "Instantaneous current modeling in a complex VLIW processor core," In ACM Transactions on Embedded Computing Systems (ACM TECS) - Special Issue on Models and Methodologies for Co-Design of Embedded Systems, vol, 4, nr. 2, pp. 415-451, May 2005.
• R. Muresan, H. Vahedi, Zhanrong Yang, S. Gregori, “Power-smart system-on-chip architecture for embedded cryptosystems”, In Proc. of CODES/ISSS, pp. 184-189,September 2005, New York, USA.
• R. Muresan, Leijian Xu, “Co-processor architecture with scaled switching activity for embedded cryptosystems”, In Proc. of IEEE MWSCAS August 2005, Cincinnati, USA.
• Haleh Vahedi, Stefano Gregori, R. Muresan, “Low-Voltage Wide-Range Built-in Current Sensing for System-On-Chip Applications”, In Proc. of IEEE MWSCAS August 2005, Cincinnati, USA.
• Xuequn Li, Haleh Vahedi, R. Muresan, S.Gregori, “An integrated current flattening module for embedded cryptosystems,” In Proc. of ISCAS 2005, Kobe, Japan, pp. 436-439.
• R. Muresan and C. Gebotys: "Current flattening in software and hardware for security applications"  In Proc. of International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS 2004, September 2004, Stockholm, Sweden.
• R. Muresan, C. Gebotys: "Current dynamics-based macro-model for power and energy simulation in a complex VLIW DSP Processor," In IEE Proceedings on Computers and Digital Techniques - Special Issue on Low-Power Systems-on-Chip, vol. 149, issue 04, pp.173-187, July 2002.
• R. Muresan, C. Gebotys: "Dynamic Power Simulation Model for VLIW DSP Processors VLSI Cores with Secure Applications," In Proc. of 11'th IFIP VLSI-SOC 2001, pp. 67-72, Dec. 2001, LIRMM Montpellier France.
• R. Muresan, C.Gebotys: "Current Consumption Dynamics at Instruction and Program Level for a VLIW DSP Processor," In  Proc. of 14'th International Symposium on System Synthesis, IEEE and ASM, pp. 130-135, Sept. 2001, Montreal.
• R. Muresan, C. Gebotys: "A Dynamic Programming Approach to Complex Allocation in a DSP Processor," In Proc. of IEEE CCECE 2001,  pp 1175 - 1183, IEEE Canada, May 2001, Toronto.

Books:

• Book Edited: Radu Muresan, "Embedded System Development and Labs for ARM, The English Edition", 2005.
• Book Chapter: C.Gebotys, R. Muresan: "Modeling Power Dynamics for an Embedded DSP Processor Core" ,  Appeared in: "SOC Design Methodologies," Edited by Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes, Kluwer Academic Publishers, Boston, July 2002, ISBN 1-4020-7148-5, Hardbound

Presentations:

• R. Muresan, "Current flattening in software and hardware for security applications"  International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS 2004, September 2004, Stockholm, Sweden

PhD Thesis:

• Radu Muresan: "Modeling and Applications of Current Dynamics in a Complex Processor Core"  PhD Thesis, University of Waterloo

MASc Thesis:

• Radu Muresan: "Dynamic Programming Approach to the Register Allocation Problem for VLES DSP Processors,"  MASc Thesis, Publisher: Waterloo Ontario: University of Waterloo, Location UW Davis, Call Number: CA2ON UW120 2001D96